a) Design a synchronous Divide-by-10 UP Counter using T flip-flop, following the steps of designing sequential circuits. (15 marks) b) For the shift register circuit shown in Figure 2, write the outputs at Qo, Q1, Q2, and Qs for each clock pulse (for 4 clock pulses) in the form of a table. (5 Marks) Q Q 0 D D D 0 ILLA Clock Figure 2