(a) Draw out the logic circuit of a synchronous SR flipflop, using only NAND gates. Derive the next state equation for this flipflop. (b) Implement the modulo 6 counter represented by the state diagram in Figure 2(a) below using JK flipflops, as specified in Figure 2(b). Implement the design using a minimum number of NAND gates. Note that the counter must return to state 0 if it enters an unused state, as indicated by the state diagram. Carry out a self-check of your design, making sure that it works as required. You do not need to draw out your circuit design. (6 (15 ma 110 011 J Q 000 CLK 101 001 K 0 111 100 (010) (ABC) JK Q(T) 00 01 0100