Based on the Verilog code of Figure 10-21, design a 2-cell boundary scan register. The first cell should be an input cell, and the second cell an output cell. Do not design the TAP controller; just assume that the necessary control signals such as shift-DR, capture-DR, and update-DR are available. Do not design the instruction register or instruction decoding logic; just assume that the following signals are available: EXT (EXTEST instruction is being executed), SPR (sample/preload instruction is being executed), and BYP (bypass instruction is being executed). Use two flip-flops for BSR1, two flip-flops for BSR2, and one BYPASS flip-flop. In addition to the control signals mentioned previously, the inputs are Pin1 (from a pin), Core2 (from the core logic), TDI, and TCK; outputs are Core1 (to core logic), Pin2 (to a pin), and TDO. Use TCK as the clock input for all of the flip-flops. Draw a block diagram showing the flip-flops, MUXes, and so forth. Then give the logic equations or connections for each flip-flop D input, each CE (clock enable), and each MUX control input.