(a) Draw the circuit described by the following Verilog design. (5 points) module HA (a,b,c,d); input a,b; output c.d; xor(c, a,b) and (d,a,b); endmodule module HAHA (a,b,c,d,e); input a,b,c; output d,e; wire r,s,t; HA ha0 (a,b,s,t); HA hal(s,c,d,r) or(e,t,r); endmodule