(a) Given the connection of three JK flip-flop output to the input of an encoder as shown in Figure 4(a). Design a synchronous counter that produces the corresponding timing diagram as shown in Figure 4(b). B j tok CLK CLK K REF K RET REF U1 9 00 CLK HCT 137 Figure 4(a) YO YI 2 Y3 Y4 YS Y6 3 17 T2 T3 T4 15 16 17 18 19 10 T11 T12 113 T14 115 116