A hypothetical accumulator processor uses one of the following 16-bit instruction formats, depending on the instruction.

1. (a) (10 points.) Draw a block diagram of this CPU, showing the sequencer, ALU, memory, and control and data registers, and use arrows to indicate how the various parts interact with each other. Assume that instructions and data are accessed using an MAR and MDR register. (This will be the Von Neumann architecture diagram of this processor, much like the one we created in class.)

2. (b) (20 points.) Give a control unit design for this processor using D-flip-flops similar to the one we designed in the lectures for Vesp 1.0. The design should include fetch, decode and execute steps in as much detail as possible.

3. (c) (20 points) Give a datapath design, also using D-flip-flops for the MDR register of this processor, clearly describing all the transfers into the MDR with the help of a typical flip-flop as we did in class by making sure that you completely specify both the data and clock inputs for that flip-flop.