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A processor has a clock rate of 2 GHz and executes a program. It has six stages as shown in the table below, with each

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A processor has a clock rate of 2 GHz and executes a program. It has six stages as shown in the table below, with each stage requiring the indicated number of cycles. Note that the time for one cycle is 1/(clock rate Instruction InstructionCalculate Fetch Execute Write Fetch Decode erands Instructions Operand 6 cycles erands 6 cycles 2 cycles 3 cycles 3 cycles 5 cycles a) What is the CPI and MIPS rate of the non-pipelined processor? b) Suppose this processor can be pipelined. What CPI, MIPS rate and speed-up of a pipelined version of this processor is possible to approach if no pipeline hazards are encountered? c) If the instructions contain 20% branch instructions that impose a 25 cycle d) Suppose we introduce branch prediction which works 90% of the time. What e) If we are able to further improve the processor by making a 2-way penalty each time they branch, what is the best CPI this system can attain? CPI can this system attain? superscalar pipeline with same branch prediction rate in d) and with no other hazards, what would the new associated CPI, MIPS rate be and what is the speed-up of this be compared to the non-pipelined processor? Assume millions of instructions are being processed. A processor has a clock rate of 2 GHz and executes a program. It has six stages as shown in the table below, with each stage requiring the indicated number of cycles. Note that the time for one cycle is 1/(clock rate Instruction InstructionCalculate Fetch Execute Write Fetch Decode erands Instructions Operand 6 cycles erands 6 cycles 2 cycles 3 cycles 3 cycles 5 cycles a) What is the CPI and MIPS rate of the non-pipelined processor? b) Suppose this processor can be pipelined. What CPI, MIPS rate and speed-up of a pipelined version of this processor is possible to approach if no pipeline hazards are encountered? c) If the instructions contain 20% branch instructions that impose a 25 cycle d) Suppose we introduce branch prediction which works 90% of the time. What e) If we are able to further improve the processor by making a 2-way penalty each time they branch, what is the best CPI this system can attain? CPI can this system attain? superscalar pipeline with same branch prediction rate in d) and with no other hazards, what would the new associated CPI, MIPS rate be and what is the speed-up of this be compared to the non-pipelined processor? Assume millions of instructions are being processed

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