A sample DDR$2$ SDRAM timing diagram is shown in Figure $2\mathrm{.}34.$ tRCD is the time required to activate a row in a bank, and column address strobe $($CAS$)$ latency $($CL$)$ is the number of cycles required to read out a column in a row. Assume that the RAM is on a standard DDR$2$ DIMM with ECC, having $72$ data lines. Also assume burst lengths of $8$ that read out $8$ bits, or a total of $64$ B from the DIMM. Assume tRCD $=$ CAS $($or CL$)$ clock$\_$frequency, and clock$\_$frequency $=$ transfers$\_$per$\_$second$/2.$ The on$-$chip latency on a cache miss through levels $1$ and $2$ and back, not including the DRAM access, is $20$ ns$.$