Above Image is page 17. Ch. 4

MIPS Assambly Language

The Single-Cycle Design

Sometimes during the manufacturing of an integrated circuit, wiresincluding control signal wiresare accidentally connected to +V or GND, resulting in a control signal that is stuck-at-1 (when connected to +V) or stuck-at-0 (when connected to GND). This is a hardware bug which will manifest itself when certain assembly language instructions are executed and do not perform the operation they are supposed to perform.

(a) Suppose the RegDst signal is stuck at 0. For each of the instructions that are implemented in the single-cycle design (using the datapath shown on p. 17 of the Ch. 4 lecture notes), list the instruction and explain if the instruction will or will not properly execute. If the instruction is affected by the hardware bug, then instead of what should happen, explain what will actually happen.

(b) Repeat exercise (a) assuming that RegDst is instead stuck at 1.

(c) Repeat exercise (a) assuming that MemToReg is stuck at 0.

(d) Repeat exercise (a) assuming that MemToReg is stuck at 1.

Instruction 125-0) Jump address [31-0] Shift eft 2 28 PC 4 [31-28] 26 PC Src M Add Mux 1 x PC Src Branch Add Add result Mux 2 PC Mux 1 Shift RegDst PC Adder Select left 2 Branch AND Branch Gate Mem Read Instruction 31-26] MemtoR Control ALUO MemWrite ALUSrc RegWrite ALU Src2 Instruction 125-21] Read Mux Read register 1 Read PC address Instruction [20-16] Read data 1 register 2 Write Read ALU ALU Result register data 2 IM result Address M Mux data Instruction [31-0] M Instruction Instruction 115 111 X memory Write data Registers Data Write Dst Reg memory 16 Instruction [15-01 Sign ALU extend control ALUOplnput Instruction (5-0]