add $t4, $t3, $t7 sub $t8, $t4, $t5 add $t9, $t8, $t4 lw $t7, 8($t4) add $t1, $t7, $t5 sub $t5, $t3, $t1 lw $t3, 4($t5)

a).For the following MIPS assembly code to be executed using the pipelined data path, identify all of the data dependencies (which register in which instruction needs the result register value from which another instruction?) and enumerate them (give them numbers as 1,2, ...). b).Which dependencies are data hazards that will be resolved via forwarding and without a stall (you can specify the number(s) from the part a)? c).Which dependencies are data hazards that will cause a stall (you can specify the number(s) from the part a)?