Assume a 16-byte cache uses a block size of 4 bytes and a 2-way set associative cache design that uses the LRU algorithm. The system address bus is 8-bit. Assume that the cache is initially empty.

First determine how many bits are used for tag, set, word fields for this cache. Then draw a table to show the structure of the cache and clearly show the tag, LRU and HITT/MISS information for each cache line after each access for the following address sequence generated by the microprocessor: 0x8D, 0xB2, 0xBF, 0x8C, 0xE9, 0x FE, 0xE9.