Assume a memory hierarchy with two levels of cache, L1 and L2.

a. What is the miss rate (MR1) for L1 if there are 75 misses per 1000 memory references?

b. What is the miss rate (MR2) for L2 if there are 50 misses per 1000 memory references?

c. What is the global miss rate of the cache hierarchy?

d. Compute the AMAT if HT1 = 1 clock cycle, HT2 = 10 clock cycles, MP2 = 200 clock cycles.

e. Compute the average stall cycles per instruction if there are 1.5 memory references per instruction. Ignore memory writes