Assume a memory model with the following specification:

memory is byte addressable

there is a single level, $4-$block cache

the cache block size is $16$ bytes

the range of memory addresses in main memory is $0$ through $255$ inclusive

the processor has a clock speed of $4GHz$

For each of the following parts, assume the cache is empty to begin, and you have the

following sequence of memory accesses:

$152,37,190,42,210,152,16,30,191,48,31,32,152,29$

$($a$)$ What addresses would be in the same block as address $210$ in main memory?

$($b$)$ Assume that the processor uses a direct$-$mapped cache. For each of the memory

accesses, indicate if it would result in a cache hit or a cache miss when the program

is executed. Justify your answers by creating a table that includes the following

headings:

The Block ID$,$ Cache Index, and Tag should all be bit sequences.

The Address should be the number from the original sequence of memory accesses.

$($c$)$ Draw a cache diagram, with the same format as Slide $71$ of Module $3,$ indicating

which block of main memory has been loaded into each block of the cache after all

the above memory access are complete. The Data column should have the Block

ID for the Mem$[]$ values. You can use the work you have done in the previous

part as justification for your answer.