Assume a single-cycle implementation of unpipelined computer that has a clock cycle time of 10 ns. The original computer functions are split into five stages to form a pipelined machine. These are IF, ID, EX, MEM, and WB. However, the computer pipelined stages do not have equal amount of execution time. The measured times for the stage are: IF 1 ns; ID 2 ns; EX 2 ns; MEM 3ns; WB 2 ns. Besides, there is a delay of 0.2 ns for the pipeline register.

What is the clock cycle time of the 5-stage pipelined machine?

If there is a stall every four instructions, what is the CPI of the new machine?

What is the speedup of the pipelined machine over the single-cycle machine?