Assume Computer XY has a $4$ GB main memory and a direct$-$mapped $($L$1)$ cache

$($there are no other cache levels and no secondary or tertiary storage$)$ with a $32$B line

size. On XY$,$ cache hits take $2$ clock cycles, and cache misses take $90$ clock cycles. Also

on XY$,$ if the CPU had disabled the cache and went directly to main memory, the main

memory access time would be $100$ cycles.

$($a$)$ If program $Z$ was run on $xY$ and had an overall miss rate of $5\%,$ what would the

average overall memory access time be in terms of CPU clock cycles?

$($b$)$ If Program A was run on XY when XY had a $32KBL1$ cache$-$ and $A$ is a program

that has a $2$ GB array of $(32$ bit$)$ integers $($and essentially no other use of memory$)$ that

is accessed in a sequential way and thus has high spatial locality of reference, what

would the overall average memory access time be in terms of CPU clock cycles? If the

cache was instead a fully associative cache, what effect would you expect that to have

on memory access time for this scenario? $($N$.$B$.$: in cache memory discussions K is not

$1000,$ instead it denotes $2^{10}(1024).)$

$($c$)$ Recompute, using the scenario in $($b$)$ except with the cache disabled, the overall

average memory access time in terms of CPU clock cycles.