Assume R1 = C3A0 0000 H, what will be the content of R1 after ASR R1, #4 instruction? Select one: 00 0000 OFC 000 10 0000 Ooc 000 Which one(s) are correct about the ARM Cortex M3 operating mode? (You may choose multiple answers) Select one or more: An interrupt is an example that results in entering to handler mode The processor enters thread mode as a result of an exception Handler mode has two states: privileged and unprivileged In thread mode, ARM is in its normal program running state After reset, it enters thread mode Which one(s) is/are correct about CISC and RISC architecture? (you may choose multiple answers) Select one or more: In CISC architecture, a single instruction performs many operations Variables-size instructions is one of the RISC features CISC requires more complex tools RISC architecture requires a bigger chip (hardware) CISC stands for Complex Instructions Set Computer Load-store architecture is used in RISC architecture Type in an instruction that performs the following expression in ARM Cortex M3 without using a multiplication instruction. R1 = R2+ 64*R3 Assume R1 = AA00 FF00 H and R2 = EOBB 88A0 H, which flags get affected after ADD R1, R2 instruction? (Assume the values are signed) Select one or more: None Z V N U