Assume that individual pipeline stages of a five-stage pipelined architecture take the following latencies: IF ID EX MEM WB 150ps 220ps250ps 300ps What would be the clock cycle time in a pipelined and a single-cycle processor (separately)? Assume that the same logics used in the five-stage pipeline architecture are used for single-cycle processor (as we reused most of the functional logics of a single- cycle processor for a five-stage pipeline architecture) a. What would be the total latency of a LW instruction in a pipelined and single-cycle processor (separately)? b