Assume that the memory address of a computer system is 32 bit. The memory location is byte addressed. Suppose we use a direct mapped cache for this computer system. The widths in a 32-bit virtual address for byte offset (in block), cache index, and cache tag are 5 bits, 11 bits, and 16 bits, respectively.

(a) How large is the address space? What size is a cache block?

(b) What is the total size of the direct mapped cache?

(c) Suppose the cache size is fixed and is fully associative now. What range of bits of the cache index, and the offset?

(d) Suppose the cache size is fixed and is 4-way associative now. What are range of bits of the cache index, and the offset?