Assume that you have a system that contains a 16-word cache ( C=16 ). Consider the following RISCV assembly code addi to, zero, 4 addi s0, zero, 0 loop: beq to, zero, done Iw tl,030 (so) Iw t2, 070(s0) Iw t3,054(so) Iw t3,050(s0) addi t0, t0, 1 j loop done: Partl: Direct Mapped Cache, b=1 word 1) Fill in the correct size for the cache fields(Assume 32-bit memory address size): 2) Place every instruction's data in the correct set in the cache. Also, determine what kind of miss the instruction faces. 3) Find the miss rate (NOTE: if the number is 88.777778, then your answer should be 88.8): (Note: number of misses includes both compulsory and the conflict misses in all iterations) Cache miss rate= %