Assume the program counter (PC) is initially equal to n. Assume that the word length of the processor is 1.

a) How many fetches are required to make PC equal to m if there are no branch instructions between n and m?

b) What is the content of the instruction register (IR) when the PCs value is n+k? Justify your answer.

Why we are not using a hundred pipeline stages if anoperation can be divided up into a hundred steps, even if we can keep the pipeline full?

Assume an operation can be divided into 1, 6, or 24 pipeline stages with no overhead and the pipeline can be kept full.

a. What degree of pipelining would provide the optimal throughput?

b. What is the throughput relative to the un-pipelined version?

What is a pipeline hazard?

Write the assembly language instructions for the following statement d = a - (b + c). Assume d is stored in R0, a in R1, b in R2 and c in R3. Use a minimal number of assembly statements and a minimal number of registers. Remember that instructions are of the following format : Instruction R1, R2, R3 where R1 and R2 are source registers and R3 is a destination register.

How long (in bits) are register ID in a system, which has 16 registers ?

What is altered in CPU when using Branching instructions?