Assume you have a 4 GHz CPU with a CPI of 1.0 (instructions on this CPU require 1.0 cycles per instruction on average) and a main memory access time of 100 ns. If the system misses 2.5% of the time, whats the new effective CPI with one level of cache?

Use the equation Total CPI = Base CPI + Memory-stall cycles per instruction

Cock cycles are required for a main memory access 400. Add to the system in a second level of cache. Now a miss in L1 can be satisfied by a hit in L2 or by main memory. This L2 cache has an access time of 5 ns for either a hit or a miss, and is large enough to reduce the miss rate to main memory to 0.8%.

Total CPI = _________________________________________ cycles per instruction