Assuming a standard 5 stage DLX pipeline with:

• Inorder issue and execution
• Separate data and instruction memory (No structural hazards)
• Forwarding is only possible from the memory stage
• It is possible to read and write to the register file in the same cycle

Pipeline the following MIPS program:

Note:

If you need to stall enter the word 'stall' in the space where you want to put it

The 5 stages are: if, id, ex, mem, wb.

• Make sure you enter them exactly as written here any divergence might lead to loss of points.

You can leave a space blank if it does not need a value.

Make sure you scroll all the way to the right until you cannot scroll any more.

Assuming a standard 5 stage DLX pipeline with: Inorder issue and execution Separate data and instruction memory (No structural hazards) Forwarding is only possible from the memory stage It is possible to read and write to the register file in the same cycle Pipeline the following MIPS program: Note: if you need to stall enter the word 'stall' in the space where you want to put it The 5 stages are: if, id, ex, mem, wb. Make sure you enter them exactly as written here any divergence might lead to loss of points. You can leave a space blank if it does not need a value. Make sure you scroll all the way to the right until you cannot scroll any more. r2,0 (1) iflid mem Iw ex wb add r3, r1, r2 add r4, r1,r3 add r5, r4, r3 add r5, r4, r5 SW r5,8 (11)