Based on the code below.

a) For each of the following instructions, for each starting at fetch1, list the names of microcode instructions used to execute the instruction. Then give the corresponding number of cycles and indicate whether the instruction returns to fetch1 or to fetch2. i) inca ii) adda $23 iii) sta [$C6] iv) suba [X+3]

b) Determine the number of bus cycles required to perform each of the following instructions. Start at 'fetch1'. Indicate if the microcode interpreter returns to 'fetch1' or 'fetch2'.

i) clra

ii) lds $FC

iii) lda [$C0]

iv) adda [X+0]

v) sta [S+0]

** Microcode interpreter for nod4.1

 ** Krista Hill - Univ. Hartford CETA - fall 2007 ** modified Dec.1.2008 - to cparts1.vhd version 1.4 ** First steps 00 init: m[0]->DX, goto jmp 01 fetch1: m[PC]->DX, PC+1->PC, goto fetch2 02 intx1: S-1->S, IID->DX, goto intx3 ** Obtain inerrupt flag 03 fetch2: m[PC]->DX, DX->IR, PC+1->PC, goto pop1+RULE1 04 intx2: PC-1->PC, goto intx1 ** Unfetch next opcode ** Implied-ACX instructions 05 pop1: m[S]->DX, S+1->S, goto pop2 06 psh1: S-1->S, goto psh2 07 nop1: goto fetch2+RULE3 08 nop2: goto fetch2+RULE3 ** Implied-ASX instructions 09 dec: r[RG]-1->r[RG], flags->ZC, goto fetch2+RULE3 0A inc: r[RG]+1->r[RG], flags->ZC, goto fetch2+RULE3 0B nop3: goto fetch2+RULE3 0C nop4: goto fetch2+RULE3 ** Implied-A 0D clra: $00->A, flags->ZC, goto fetch2+RULE3 0E inva: not A -> A, flags->ZC, goto fetch2+RULE3 0F nega: -A -> A, flags->ZC, goto fetch2+RULE3 10 nop5: goto fetch2+RULE3 ** Implied-PC 11 rts: m[S]->DX, S+1->S, goto jmp 12 rti1: m[S]->DX, S+1->S, goto rti2 13 swi1: PC-1->PC, goto swi2 ** Unfetch the next opcode 14 nop6: goto fetch2+RULE3 ** Immediate-ACX 15 andimm: r[RG] and DX -> r[RG], flags->ZC, goto fetch1+RULE3 16 orimm: r[RG] or DX -> r[RG], flags->ZC, goto fetch1+RULE3 17 cmpimm: r[RG] - DX, flags->ZC, goto fetch1+RULE3 18 nop7: goto fetch1+RULE3 ** Immediate-ASX 19 addimm: r[RG]+DX->r[RG], flags->ZC, goto fetch1+RULE3 1A subimm: r[RG]-DX->r[RG], flags->ZC, goto fetch1+RULE3 1B ldimm: DX->r[RG], flags->Z, goto fetch1+RULE3 1C nop8: goto fetch1+RULE3 ** Immediate-jumps1 1D jmp: DX->PC, goto fetch1+RULE3 1E jne: goto jmpyes + (Z = 1) 1F jeq: goto jmpno1 + (Z = 1) 20 jlo: goto jmpno1 + (C = 1) 21 jhi: goto jmpyes + (C or Z = 1) 22 jls: goto jmpno1 + (C or Z = 1) 23 jhs: goto jmpyes + (C = 1) 24 jsr1: S-1->S, goto jsr2 ** direct handlers 25 dir-rd: m[DX]->DX, goto anddir+RULE2 26 dir-st: r[RG]->m[DX], flags->Z, goto fetch1+RULE3 ** indexed handlers 27 inds-rd: DX+S->ND, goto nd-rd 28 indx-rd: DX+X->ND, goto nd-rd 29 inds-st: DX+S->ND, goto nd-st 2A indx-st: DX+X->ND, goto nd-st 2B nd-rd: m[ND]->DX, goto anddir+RULE2 2C nd-st: r[RG]->m[ND], flags->Z, goto fetch1+RULE3 ** execute direct and indexed instructions 2D anddir: r[RG] and DX -> r[RG], flags->ZC, goto fetch1+RULE3 2E ordir: r[RG] or DX -> r[RG], flags->ZC, goto fetch1+RULE3 2F cmpdir: r[RG] - DX, flags->ZC, goto fetch1+RULE3 30 nop9: goto fetch1+RULE3 31 lddir: DX -> r[RG], flags->Z, goto fetch1+RULE3 32 nouse1: ** store done at dir-st 33 adddir: r[RG]+DX -> r[RG], flags->ZC, goto fetch1+RULE3 34 subdir: r[RG]-DX -> r[RG], flags->ZC, goto fetch1+RULE3 ** Some instructions need more cycles 35 pop2: DX->r[RG], goto nfetch 36 psh2: r[RG]->m[S], goto fetch2+RULE3 37 rti2: DX->C, m[S]->DX 38 rti3: S+1->S, goto jmp ** Finish software interrupt 39 swi2: S-1->S 3A swi3: S-1->S, PC->m[S] 3B swi4: $01->ND, C->m[S] 3C swi5: $00->C, m[ND]->DX, goto jmp ** Prepare for an interrupt 3D intx3: S-1->S, PC->m[S] 3E intx4: $01->PC, C->m[S], 3F intx5: DX and $1F -> C, m[PC]->DX, goto jmp ** Final instructions needing more cycles 40 jsr2: PC->m[S], DX->PC, goto fetch1+RULE3 41 jmpno1: goto fetch1+RULE3 42 jmpyes: DX->PC, goto fetch1+RULE3 43 jmpno2: goto fetch1+RULE3 44 nfetch: PC-1->PC, goto fetch1+RULE3