Path effort - Suggested Question In driving a digital bus, the emphasis is on reducing the number of stages needed to drive a load. For this problem assume that polarity at the driving node does not matter and the plan is to use inverters only. For the capacitive load shown in Figure 1 you need to show how you can decide on the number of stages needed in the buffer stage to result in minimum gate delay. (Hint: Use the given formulae and tables given in the lecture slides). (a) Calculate the path effort for the possible number of stages that can be used. (b) Calculate the minimum number of stages that can be used to result in minimum delay in terms of T. Vin of Buffer stage Figure 1: logic network. Two input NOR gate NOR2 Vou 375 C out