Complete the table for a 4 bits synchronous binary counter and find out the clock frequency Give the output expression Z for the 8-to-1 MUX shown below. Synchronous Counter design: Complete the design of a three bit counter for the following state transition diagram. Then: a) Complete in the table the missing sequences and have all PRESENT states and their NEXT states available. b) Using the j-K flip-flop excitation table for the complete circuit excitation table c) Have the K-maps per each flip-flop and obtain a simplified expression for FF' inputs. d) Counter Circuit Implementation