Computer architecture

Question 3) All the threads in an Simultaneous Multithreading (SMT) processor share a data cache and a single instruction cache.

a) How could this potential hurt performance of the threads running on the processor?

b) Under what circumstances could it help?

c) Suggest a way that the architecture could limit the damage and maximize the gain.

d) Would you expect the benefits to larger or smaller for the instruction cache or the data cache? Why?