Consider 512Kx8bits dynamic RAM chips where the memory access time is 2/3 of the memory cycle time. These chips have an Address Bus, a bi-directional Data Bus, a Read/Write control line and a Chip Select line.

(a) Draw the diagram of a memory organization that will contain 4 megabytes, will have a 32-bit bi-directional data bus and will yield one word (32-bits) every access time if words are read from consecutive memory locations (in bursts). Clearly show and explain the number of memory chips used, how your design is capable of reading one word every memory read access time, and which bits in the address are used to select a word from your memory organization.

(b) For this memory organization, can one write a block of consecutive words faster than one every memory cycle time?

(c) Suggest a timing such that words are read faster than one every access time (assume that data appears on the memory chips data bus instantaneously at the time it becomes available).