Consider a 2 mm long, 1.0um-wide metal wire. The sheet resistance is 0.05 22/ and the capacitance is 0.3 fF/um. (20 point) a) Construct a 3-segment -model for the wire. b) Estimate the delay when a 2-input NAND gate with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter is deriving a 2x inverter with the 2 mm wire. The gate capacitance is C=1fF/um, the effective resistance is R=2.0 kOhm*um, the device width W=0.4um for nMOS transistor of unit inverter.