6. A NAND gate with eight inputs is required. For each of the following cases, minimize the number of gates used in the multiple-level result: 6.a Design the 8-input NAND gate using 2-input : NAND gates and NOTgates. Answer: 8-input NAND = (x,x,x3X4X3XgX7Xg)' %3D = ((x,x,)"(x3x4)"(x3,)"(x,*g)")' = ([(x1x2)"(x3x4)"]"[(x3*6)"(x7Xg)"]")' 6.b Design the 8-input NAND gate using 2-input NAND gates, 2-input NOR gates, and NOT gates only if needed. Answer: 8-input NAND = ([(x,x2)"(x3x4)"]"[(x3x6)"(x7xg)"]")'| = ([(x,x2)' + (x3X4)TI(xs*6)' + (x,xg)T) Iaro 6.c Compare the number of gates used in (a) and (b). Answer: The circuit in part (b) has 6 fewer gates (including the NOT gates)