Consider a 4 way associative set of size 8 (blocks). The cache has two sets: set 0 and 1. It uses LRU for cache misses and is initially empty. Show the contents and miss/hit of the cache at every step of the following sequence of memory accesses

1. Consider a 4-way set associative cache of size 8 (blocks). The cache has two sets (set0 and set1). It uses LRU for block replacement on cache misses. Initially, the cache is empty. Show the contents and miss/hit of the cache at each step of the following sequence of memory accesses: block00 block 04 block 02 block 08 block04 block 12 block 04 block 08