Consider a 5-stage IF, ID, EX, MEM and WB pipeline as specified in Figure 4.46. Assume perfect branch prediction (no stalls due to control hazard). Data forward is used. In the case of data hazards, we need to stall the execution.

a) Draw the pipeline execution diagram. Make sure to indicate stalls and show data forwarding from a source stage to a destination stage.

b) How many clock cycles are needed to execute these instructions? [Hint: the instructions do terminate.]

I1: addi $s0, $zero, 2

I2: add $s1, $a0, $zero

I3: loop: lw $t0, 0($s1)

I4: lw $t1, 10($t0)

I5: add $s1, $t0, $t1

I6: addi $s0, $s0, -1

I7: bne $s0, $zero, loop

I8: add $v0, $s1, $zero

Figure 4.46:

An example of a Pipline Execution Diagram: