Consider a cache with 2 word blocks, which is byte addressable.

a) If this cache holds 32 KB of data, how many index bits does it need and why?

b) What is the total cache size that holds these data considering that it uses 3-bit word offset and 1-bit block offset (do not forget about the Valid bits it uses);

c) We decide to increase the amount of data the cache can hold to 64 KB. Each block this time has 16 words. How many index bits does this new cache have and why?

d) What is the total size of this new cache, if it uses 3-bit word offset and a number of block offset bits needed by the MUX to determine which word is needed by the pipeline?

e) Draw the cache in question d.