Consider a Direct Mapped cache with 32-bit memory address reference word addressable. Assume a 2 word block and a Cache size of 8 locations. Each location has one block. Starting with an empty cache assume the following memory address references in the corresponding order Word Addresses in Main Memory Address 3180 43 2 191 88 190 14 190 | 14 | 181 44 186 253 To what address in cache is the underlined reference above map to? Select one: O a. 4 O b. 7 Oc5 O d. 2 O e 6