Consider a system with a two-level cache having the followingcharacteristics: L1 cache has an access time of 1 clock cycle withan average hit rate of 95%; L2 cache has an access time of 5 clockcycles (after L1 miss) with an average miss rate of 10%. If L2misses take 40 clock cycles, what would be the average memoryaccess time in clock cycles? If the clock rate is 1 GHz, what wouldit be in seconds?