Consider an L1 cache that has 16 sets, is direct-mapped (1-way), and supports a block size of 16 bytes. For the following memory access pattern (shown as byte addresses), show which accesses are hits and misses. For each case, indicate the set number. 0, 8, 16, 24, 32, 40, 48, 256, 28, 8, 36, 12, 20, 260.