Consider the 2-Stage JFET in figure Sa. V 10u SIMO 340 Wat oss-10 Vp-4V Somo 20V IMG IMO Figure Sa FIND D 100 hi ind a) Name the configurations in both stages. (2) (b) Find the input impedance 23 of first stage and also find the output impedance of the second stage. (Both transistors have an rdie (). (c) Calculate the voltage gain for stage 1. (6) Calculate the voltage gain for stage 2 [3] (e) if the input voltage signal is V-5sin auf mV, sketch the output voltage signal Vo. [3] (f) The overall voltage gain you calculated above is ideal. What do you expect from the practical voltage gain of the circuit in figure 5a compared to the ideal? Explain your (21 > reasons 121 (3)