Consider the delays from the table below. Now suppose that the ALU were 20% faster. Would the cycle time of the pipelined ARM processor change? What if the ALU were 20% slower?

Element Register clk-to-Q Register setup Multiplexer ALU Decoder Memory read Register file read Register file setup Delay (ps) 40 50 25 120 70 200 100 60 Parameter setup ALU tdec men tR Fread RFsetup