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Consider the exccution of this MIPS instruction $ w $ 5 1 , 1 6 ( $ s 0 ) in the single cycle data

Consider the exccution of this MIPS instruction $

w

51, 16 (

s 0)

in the single cycle data path diagram. Which instruction bits are read by the processor as the source register for the address that will be offset by the immediate value?

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