Consider the execution of the following loop.

Loop: l.d f2,0(r1)

add.d f4,f2,f2

l.d f6,0(r2)

add.d f6,f2,f6

add.d f6,f6,f6

s.d f6,0(r2)

addi r2,r2,#-8

addi r1,r1,#-8

bnez r1,Loop

Use a MIPS pipeline extended with a two-issue Tomasulos algorithm with speculation. Assume two instructions can be issued on every clock cycle, even if they are dependent except when both are floating point operations. Branches are single-issue. Assume one integer functional unit is used for both ALU operations and effective address calculations. Assume that a separate pipelined FP functional unit for each operation type. Assume that there is dynamic branch prediction hardware and a separate functional unit to evaluate branch predictions/conditions. Assume that branches single issue. Assue there are two CDBs. Assume that Issue and Write take 1 clock cycle. Integer operations take one cycle in their execution unit, and FP additions take 3 cycles in theirs. Fill in the table below with the appropriate clock cycle numbers.

teration instructions issues executes read memorywrite commit number access atCDB at 1l.d f2,0(rl) add.d f4,f2,f2 1 l.df6,0(r2) add.d f6,f2,f6 add.d f6,f6,f6 1 s.df6,0(r2) addi addi r2,r2,#-8 r1,r1,#-8 bnez rl,Loop add.d f4,f2,f2 2 L.df6,0 (r2) add.d f6,f2,f6 add.d f6,f6,f6 2 s.df6,0(r2) 2 2 2 2 2 addi addi r2,r2,#-8 r1,r1,#-8 bnez rl,Loop teration instructions issues executes read memorywrite commit number access atCDB at 1l.d f2,0(rl) add.d f4,f2,f2 1 l.df6,0(r2) add.d f6,f2,f6 add.d f6,f6,f6 1 s.df6,0(r2) addi addi r2,r2,#-8 r1,r1,#-8 bnez rl,Loop add.d f4,f2,f2 2 L.df6,0 (r2) add.d f6,f2,f6 add.d f6,f6,f6 2 s.df6,0(r2) 2 2 2 2 2 addi addi r2,r2,#-8 r1,r1,#-8 bnez rl,Loop