Consider the following assembly code: Instruction Description LDRI, 45(R2) Read data from memory and store in RI. Memory address is calculated by adding 45 to the content of R2 ADD R7, RI, RS Add contents of RI and Rs and store to R7 XOR R2, R7, R7 Logical Ex-OR between contents of R7 with R7 and store result in R2 BEZ R2, Target Jump to Target if R2 is Zero LD R3, 50(R4) Read data from memory and store in R3. Memory address is calculated by adding 50 to the content of R4 LD RS, 45(R6) Read data from memory and store in R5. Memory address is calculated by adding 45 to the content of R6 ADD RIO, RS, R3 Add contents of R5 to R3 and store in RIO Target: AND R2, R3, RS Logical AND between contents of R3 & RS. Store result to R2 ADD R10, R8, R2 Add contents of R2 and R8 and store to R10 END Use five-stage pipeline containing Fetch, Decode, Memory read, Execute, Write-back units, show the execution of above instructions. Data dependencies and control hazards, if detected must be resolved by delaying the pipeline as required. Assume that a multi-port RAM is used with the CPU running at 1GHz and each section requires 3 clock cycles. Calculate the execution time