Consider the following assembly fragment (assume no branch delay slots):

0 start : ori $t0 , $0 , 0x0008

1 ori $t1 , $0 , 0x0003

2 addi $t2 , $0 , $0

3 loop : and $t3 , $t1 , $t0

4 beq $t3 , $0 , skip

5 addi $t2 , $t2 , 1

6 skip : addi $t0 , $t0 , -1

7 bne $t0 , $0 , loop

What is the final value stored in $t2?

How many times does line #5 execute?

On the code above mark the true (read-after-write) dependencies between instructions.

Assuming the MIPS 5-stage with no forwarding, branch resolution in the Exe stage and a branch-not-taken policy, during what cycle does the bne in line #7 get fetched the first time?

Repeat the previous problem assuming forwarding logic and the branch resolution is moved to the Reg stage.

If a single-bit, dynamic branch predictor was used to predict these branches, what would be the misprediction percentage for each of these branches (examine them individually). Assume that each branch has its own predictor and all are reset to 0 (not-taken) at the start of the program.

If a two-bit, dynamic branch predictor was used to predict these branches, what would be the misprediction percentage for each of these branches (examine them individually). Assume that each branch has its own predictor and both are reset to 01 (not-taken) at the start of the program.

Imagine that the MIPS ISA provided a way for the compiler to insert a static branch prediction for each branch. This form of branch prediction typically takes the form of branch hint bits which tell the microarchitecture that the compiler/profiler thinks that a given branch will either be taken or not-taken more frequently than not. Assuming the compiler can analyze or profile the code to insert the best static prediction possible, what would be the misprediction percentage for each of these branches?

Rewrite the assembly code to include branch delay slots. Remember that NOPs must be inserted if there are no other instructions to fill the branch delay slot.