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Consider the following instruction: AND Rd , Rs , Rt Interpretation: Reg [ Rd ] = Reg [ Rs ] AND Reg [ Rt ]
Consider the following instruction:
AND Rd Rs Rt
Interpretation: RegRd RegRs AND RegRt
What are the values of the control signals generated by this control function?
RegDst
ALUOp b
Branch
MemWrite
MemRead
ALUSrc
MemtoReg
RegWrite
Which resourcesblocks perform useful function for this instruction?
Which resourcesblocks produce outputs, but their outputs are not used for this instruction? Which produce no outputs?
Problem :
The basic singlecycle MIPS implementation in the provided figure can only implement some instructions. New instructions can be added to an existing instruction set architecture ISA but the decision whether or not to do that depends, among other things, on the const and complexity the proposed addition introduces into the processor datapath and control. For this problem, refer to the following proposed new instruction:
LWI RtRdRs
Interpretation: RegRt MemRegRd RegRs
Which existing blocks, if any, can be reused for this instruction?
Which new functional blocks if any are needed for this instruction?
What new signals do we need if any from the control unit to support this instruction?
When processor designers consider a possible improvement to the processor datapath, the decisions usually depends on the costperformance tradeoff. For this problem, assume that we are starting with the datapath shown in the provided figure, the different elements have latencies and costs as show in the provided table image
Consider adding a multiplier to the ALU. This addition will add ps to the latency of the ALU and will add a cost of to the ALU. The result will be fewer instructions executed because we will no longer need to emulate MUL instructions.
What is the clock cycle time with and without this improvement?
What is the speedup achieved by adding this improvement?
Compare the costperformance ratio with and without this improvement
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