Consider the following instruction sequence executing on the 5-stage MIPS pipeline of form IF, ID, EX, MEM, WB.

LW $1, 8($10)

LW $2, 12($11)

SUB $3, $2, $4

ADD $5, $14, $13

AND $12, $1, $5

SW $12, 100($6)

(a) Assume that the pipeline does not use any forwarding. Complete the following pipeline execution diagram for the above instruction sequence, showing the flow of instructions through the pipeline during each clock cycle. Indicate any necessary stalls on the pipeline diagram. How many cycles does it take to complete execution of the instruction sequence?

Instruction/cycle	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16
LW $1, 8($10)	IF	ID	EX	MEM	WB
LW $2, 12($11)
SUB $3, $2, $4
ADD $5, $14, $13
AND $12, $1, $5
SW $12, 100($6)

(b) Now Assume that all possible forwarding paths have been added to the pipeline. Redraw the pipeline execution diagram below. In the diagram show forwarding by arrows. How many cycles does it take to finish the instruction sequence?

Instruction/cycle	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16
LW $1, 8($10)	IF	ID	EX	MEM	WB
LW $2, 12($11)
SUB $3, $2, $4
ADD $5, $14, $13
AND $12, $1, $5
SW $12, 100($6)