Consider the following instruction sequence that executes on the pipeline with both a hazard unit as well as a forwarding unit: ori $4,$0,2 loop: add $6,$7,$8 and $9,$4,$7 bne $4,$0,loop srl $4,$4,1 addi $3,$0,1 sll $3,$3,1 a) Without branch prediction, during which clock cycle would the sll instruction complete the write-back stage if the ori is fetched in cycle 1?

b) If branch predictions occur in the decode stage, during which clock cycle would the sll instruction complete if the ori is fetched in cycle 1 and the branch is always predicted to be taken?