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Consider the following sequence of instructions. addi x 1 1 , x 1 2 , 5 add x 1 2 , x 1 1 ,

Consider the following sequence of instructions.
addi x11, x12,5
add x12, x11, x14
ld x14,32(x11)
add x12, x14, x11
Assume that WAR and WAW hazards (if any) are resolved using advanced computer architecture techniques.
Using a data forwarding hardware, how many clock cycles would it take to execute the above code correctly in a five stage RISC-V pipeline.
Note: Dependence has a different inpretation than hazards. A dependence condition arises when two instructions are dependent on one another in the use of their register operands. A hazard, on the other hand, is a condition that may result in error when executing dependent instructions.

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