Question
Consider the following sequence of instructions: (I1) beq $9, $10, EXIT (I2) add $9, $11, $12 (I3) lw $16, 12($9) (I4) sw $16, 16($19) (I5)
Consider the following sequence of instructions:
(I1) beq $9, $10, EXIT
(I2) add $9, $11, $12
(I3) lw $16, 12($9)
(I4) sw $16, 16($19)
(I5) sw $18, 0($11)
(I6) add $4, $0, $0
(I7) add $5, $0, $0
Assume the following: There are no stalls in the code above 5 stage pipeline (IF, ID, EX, MEM, WB) is available Each instruction executes every stage No branch stalls Draw the pipeline stage table and identify instructions and stages in the table.
What is the Pipeline Instructions Latency?
What is the Pipeline Instructions Throughput?
What is the Pipeline Instructions Concurrency?
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