Consider the following sequence of MIPS instructions executed on the 5-stage pipeline lw $2, 0($1) add $4, $2, $3 sub $4, $4, $5 sw $4, 0($1) Simulate executions of this sequence of instructions in the following table with hazard detection and data forwarding. You need to insert the execution sequence according to the following guideline. You should use IF, ID, EX, MEM, WB to indicate the respective stages of an instruction at a particular cycle. If a hazard is detected, you should mark stall in the respective cycle and resume the pipeline stages after the stall. If forwarding is detected, you need to draw an arrow (->) from the pipeline register (stage) of the instruction which produces the data to the correct pipeline stage of the instruction which consumes the data. It is IMPORTANT to know that similar to data forwarding to the EX stage described in Section 4.7 of the textbook, data forwarding can be done to the MEM stage for store instruction (sw). This MEM-stage forwarding occurs when an early instruction (such as R-type) produces a result for the sw instruction to store the result into data memory in the MEM stage. Instruction CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 lw $2, 0($1) add $4, $2, $3 sub $4, $4, $5 sw $4, 0($1)