Consider the following Verilog code for a T flip$-$flop. What is the correct code for the

missing part?

module t flip$\_$flop $($

input wire clk$,$d

input wire reset,

input wire

output reg q

always @$($posedge clk or posedge reset$)$

if $($reset$)$ a

q $<=1\text{'}$b$0$;

else

$//$ Missing code here

endmodule

O a$.$ q $<=$ t;

O b$.$ None of the given options

O c$.$ q $<=$ t$^$q;

O d$.$ q $<=!$q;

O e$.$ The code is complete.