Consider the MDR of the MIPS hardwired logic architecture for an instruction cycle as single as well as multiple machine cycles. Describe the complete flow of information and on two implementation cases single and multiple machine cycles for the addition instructions:

add $4, $5, $6 add $4, $5, -128

Specifically, for each of the two commands separately, report all the values of control signals produced, as well as the microfunctions performed in each subunit of the MDR , in the order they are executed, whether they are useful for the particular command or not a fact that you are asked to report. Also, write down the prices of information reaching each subunit, including the PC, and each multiplexer. Finally, for the case of multiple engine cycles, report the entries of the A, B, C, IR and DR registers that occur and the values that are written. Consider that at the beginning of each instruction cycle the registers $4, $5 and $6 contain the values 0x6a4, 0xb9 and 0xffff927 respectively, while PC contains the value 0x14810a3c.

What if the $5 register had a value of 0x80000000?