Delay in multiplier arrays is investigated in this problem.

(a) Calculate the delay, in terms of full-adder block delays, in producing product bit p7 in

each of the 4 4 multiplier arrays in Figure 9.16. Ignore the AND gate delay to generate

all miqj products at the beginning.

(b) Develop delay expressions for each of the arrays in Figure 9.16 in terms of n for the n n

case, as an extension of part (a) of the problem. Then use these expressions to calculate

delay for the 32 32 case for each array.

m393 FA P7 P6 m290 m1390 m3q1 m 191 m2q1 FA FA FA. m392 m292 m 192 moq2 FA FA FA FA m 193 m2q3 moq3 FA FA FA (a) Ripple-carry array m 190 moq1 FA moq0